(1) Field of the Invention
The present invention relates to a Complementary Metal Oxide Semiconductor (CMOS) solid-state imaging device.
(2) Description of the Related Art
A conventional solid-state imaging device shall be described with reference to FIG. 1.
FIG. 1 illustrates a circuit configuration for one pixel in the conventional solid-state imaging device according to Patent Literature 1: Japanese Unexamined Patent Application Publication No. 2004-159155. As illustrated in FIG. 1, the pixel includes a switching circuit 900 and a photodiode 910, and the switching circuit includes a transfer transistor TRt, a capacitor C, a reset transistor TRr, a sense amplifier transistor TRa, and a switching transistor TRs.
Along a pixel row, an address line A1, a transfer control line T and a reset line R are provided. The transfer control line T and the reset line R are connected to a vertical scanning circuit (not illustrated). Along a pixel column, a signal line L1 and a bias line B are provided.
Next, a conventional solid-state imaging device shall be described with reference to FIG. 2. As illustrated in FIG. 2, when assuming a global shutter input mode, which is a short-time exposure method, the vertical scanning circuit sends all-reset signal in high (H) level for an instant simultaneously to the reset lines in all rows in response to an input of a trigger signal. At the same time, the vertical scanning circuit sends all transfer signal in H level to transfer control lines T in all rows. With this, the pixel signal accumulated in the photodiodes 910 and capacitors C in all pixels is discharged through the reset transistors TRr, resetting the photodiodes 910 and the capacitors C in all pixels.
Subsequently, the vertical scanning circuit resends the all transfer signal in H level for an instant before negating the vertical synchronization signal. With this, the transfer transistor TRt is turned off for a short period of time, and the photodiodes 910 in all of the pixels are exposed to light in the meantime. In all of the pixels, the pixel signals move to the capacitors C from the photodiodes 910 to the capacitors C through the transfer transistor TRt when resending all of the transfer signals, and the pixel signals are temporarily accumulated in the capacitors C.
Subsequently, the vertical scanning circuit sends an address line selection signal for each row. With this, the pixel signal obtained by exposing all of the pixels to light is sent to the sense amplifier transistor TRa and amplified. Furthermore, the amplified pixel signal is sent to the signal line L1 through the switching transistor TRs, and an image signal can be obtained.